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Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5{10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area{array pad router which di ers from other approaches in that no additional metal layer is added (unless needed) and no redi...
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ژورنال
عنوان ژورنال: Proceedings of the National Academy of Sciences
سال: 1946
ISSN: 0027-8424,1091-6490
DOI: 10.1073/pnas.32.1.5